Hybrid technology combines III-V tunnel FETs and MOSFETs

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most conventional and widely used type of transistors. One of their major limitations is their high power inefficiency, which is due to their inability to reduce the voltage supply while simultaneously limiting the off-state leakage current. A novel and alternative type of device called a tunnel field-effect transistor (TFET) can overcome this limitation by leveraging quantum mechanical tunneling instead of thermionic emission. TFETs, particularly those with a III-V heterostructure, require less than 60 mV of gate voltage swing to induce a variation of one order of magnitude in the drain current at ambient temperatures. Despite their lower power consumption, TFETs have not yet achieved the remarkable speed and energy efficiency of MOSFETs at higher drive voltages.

Researchers at IBM Research Europe and at École Polytechnique Fédérale de Lausanne (EPFL) have recently developed the first silicon-based hybrid device that combines III-V tunnel FETs and conventional MOSFETs. The technology they developed, presented in a paper published in Nature Electronics, combines the advantages of the two different transistor designs. The new platform developed by Convertino and her colleagues exploits the synergies between tunnel FETs and MOSFETs, as it allows users to implement hybrid logic blocks tailored to the unique specifics of each type of device. In initial evaluations, the scaled III-V hybrid TFET-MOSFET device achieved a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices.

The remarkable performance achieved by the researchers' device is in part due to their introduction of a self-aligned source-replacement step. In their platform, in fact, the position of the GaAsSb source is determined by digital etching, a process that allows them to remove material with a control in the nanometer range. Convertino and her colleagues were the first to effectively demonstrate the integration of an in-plane heterojunction tunnel FET in an advanced hybrid platform using replacement metal-gate and spacer technologies. In the future, the technology they created could enable the development of faster and more efficient electronic devices that combine the advantages associated with TFET and MOSFET transistors.

https://techxplore.com/news/2021-03-hybrid-technology-combines-iii-v-tunnel.html